1. Field
Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a semiconductor memory device that can support a parity operation mode.
2. Description of the Related Art
FIG. 1 is a block diagram illustrating a layout of a plurality of banks and peripheral regions in a conventional semiconductor memory device.
Referring to FIG. 1, a conventional semiconductor memory device includes a plurality of banks BANK0, BANK1, BANK2, and BANK3 and peripheral regions DQPERI and ACPERI.
The plurality of banks BANK0, BANK1, BANK2, and BANK3 store data and, as shown in FIG. 1, occupy more circuit area than the peripheral regions DQPERI and ACPERI. The plurality of banks BANK0, BANK1, BANK2, and BANK3 are disposed symmetrically with respect to one another and respectively occupy the corners of the semiconductor memory device.
The first peripheral region DQPERI is disposed on the semiconductor memory device between the first and second banks BANK0 and BANK1, and the second peripheral region ACPERI is disposed on the semiconductor memory device between the third and fourth banks BANK2 and BANK3. The first peripheral region DQPERI includes circuits involved in data input/output operations, and the second peripheral region ACPERI includes circuits involved in control operations of the semiconductor memory device. In addition, the semiconductor memory device includes a plurality of pads. The pads may include a data input/output pad (DQ), a command input pad (CMD_PAD), and an address input pad (ADDR_PAD).
Furthermore, a clock input pad CLK_PAD is disposed at the center of the semiconductor memory device such that the clock input pad CLK_PAD is positioned at a first distance from the plurality of respective banks BANK0, BANK1, BANK2, and BANK3. The position of the clock input pad CLK_PAD is to prevent the occurrence of a skew when an operating clock CLK inputted through the clock input pad CLK_PAD is transferred to the plurality of respective banks BANK0, BANK1, BANK2, and BANK3.
FIG. 2 is a block diagram illustrating a detailed layout of a clock input pad and a second peripheral region in the conventional semiconductor memory device shown in FIG. 1.
Among the component elements of the conventional semiconductor memory device, the dock input pad CLK_PAD is positioned at the center of the semiconductor memory device at the first distance from the plurality of respective banks BANK0, BANK1, BANK2, and BANK3, and the second peripheral region ACPERI is defined on the right side of the clock input pad CLK_PAD. Referring to FIG. 2, the clock input pad CLK_PAD and the second peripheral region ACPERI are illustrated, and as an example, the clock input pad CLK_PAD is illustrated to the left of the command input pad CMD_PAD.
In detail, in the second peripheral region ACPERI, a command input pad CMD_PAD and a command decoder 240 are disposed most adjacent to the clock input pad CLK_PAD. Accordingly, the command input pad CMD_PAD and the command decoder 240 are positioned at the first distance from the plurality of respective banks BANK0, BANK1, BANK2, and BANK3.
Because the command input pad CMD_PAD and the command decoder 240 are positioned most adjacent to the clock input pad CLK_PAD, which is positioned at the center of the semiconductor memory device, the occurrence of a skew may be prevented when a command signal EXT_CMD_SIG applied through the command input pad CMD_PAD is decoded through the command decoder 240 and subsequently a resultant signal DEC_CMD_SIG is transferred to the plurality of respective banks BANK0, BANK1, BANK2, and BANK3.
For reference, since a procedure that outputs the command signal EXT_CMD_SIG as an internal command signal INT_CMD_SIG is performed in synchronization with the operating clock CLK, as shown in the drawing, a flip-flop F/F for outputting the external command signal EXT_CMD_SIG as the internal command signal INT_CMD_SIG in response to the operating clock CLK is provided between the command input pad CMD_PAD and the command decoder 240. The external command signal EXT_CMD_SIG and the internal command signal INT_CMD_SIG are substantially the same signal except that the internal command signal INT_CMD_SIG is synchronized with the operating clock CLK. Therefore, unless it is necessary to distinguish the internal command signal INT_CMD_SIG and the external command signal EXT_CMD_SIG from each other, the internal command signal INT_CMD_SIG and the external command signal EXT_CMD_SIG will not be distinguished from each other in the following descriptions and will be referred to as a command signal INT_CMD_SIG.
As shown in FIG. 2, an address input pad ADDR_PAD in the second peripheral region ACPERI is disposed on the right side of the command input pad CMD_PAD such that the address input pad ADDR_PAD is positioned closer than the first distance to the third and fourth banks BANK2 and BANK3 among the plurality of banks BANK0, BANK1, BANK2, and BANK3 and further than the first distance from the first and second banks BANK0 and BANK1.
Accordingly, when an address signal EXT_ADDR_SIG is inputted through the address input pad ADDR_PAD and is transferred to the plurality of banks BANK0, BANK1, BANK2, and BANK3, a time that elapses for transferring the address signal EXT_ADDR_SIG to the third and fourth banks BANK2 and BANK3 among the plurality of banks BANK0, BANK1, BANK2, and BANK3 is different than a time that elapses for transferring the address signal EXT_ADDR_SIG to the first and second banks BANK0 and BANK1.
Even when the time that elapses for transferring the address signal EXT_ADDR_SIG to the plurality of banks BANK0, BANK1, BANK2, and BANK3 may be different, no substantial issues are caused in the operation of the semiconductor memory device because the plurality of banks BANK0, BANK1, BANK2, and BANK3 respectively have separate address decoders (not shown) for decoding the address signal EXT_ADDR_SIG.
For reference, since a procedure that outputs the address signal EXT_ADDR_SIG as an internal address signal INT_ADDR_SIG is performed in synchronization with the operating clock CLK, as shown in the drawing, flip-flops F/F for outputting the external address signal EXT_ADDR_SIG as the internal address signal INT_ADDR_SIG in response to the operating clock CLK are provided over the address input pad ADDR_PAD. The external address signal EXT_ADDR_SIG and the internal address signals INT_ADDR_SIG are substantially the same signal except that the internal address signals INT_ADDR_SIG are synchronized with the operating clock CLK. Therefore, unless it is necessary to distinguish the internal address signal INT_ADDR_SIG and the external address signal EXT_ADDR_SIG from each other, the internal address signal INT_ADDR_SIG and the external address signal EXT_ADDR_SIG will not be distinguished from each other in the following descriptions and will be referred to as an address signal INT_ADDR_SIG.
As shown in FIG. 2, the number of flip-flops F/F provided over the address input pad ADDR_PAD is greater than the number of flip-flop F/F provided over the command input pad CMD_PAD. The difference in the number of flip-flops F/F occurs because the bit number of the address signal INT_ADDR_SIG applied through the address input pad ADDR_PAD is significantly greater than the bit number of the command signal INT_CMD_SIG inputted through the command input pad CMD_PAD, and accordingly, the area occupied by the address input pad ADDR_PAD is larger than the area occupied by the command input pad CMD_PAD.
Meanwhile, in the conventional semiconductor memory device described above with reference to FIGS. 1 and 2, a parity operation component element for detecting an error occurring in the command signal INT_CMD_SIG applied through the command input pad CMD_PAD and for controlling the operation of the semiconductor memory device is not included. Thus, in the event that the error occurs in the command signal INT_CMD_SIG applied through the command input pad CMD_PAD, the semiconductor memory device is likely to perform an erroneous operation as the semiconductor memory device operates with the erroneous command signal INT_CMD_SIG.